The present invention relates to a semiconductor memory and, more particularly, to a technique which may effectively be utilized for, for example, a dual-port memory or the like which has both a random access port and a serial access port.
As a picture frame buffer memory used for displaying characters or figures on the screen of a CRT (cathode-ray tube), for example, a dual-port memory is employed.
A conventional dual-port memory, is, as exemplarily shown in FIG. 4, provided with a data register DR1 in which bits are respectively provided in correspondence with complementary data lines in a memory array M-ARY, and a data selector DSL1 which selectively connects the bits in the data register DR1 to a serial input/output complementary common data line CDS1. The data selector DSL1 is composed of switching MOSFETs which are respectively supplied with corresponding data register select signals from a pointer PNT. These data register select signals are sequentially formed in such a manner that a shift signal of the logic "1" which is set in the pointer PNT is shifted in accordance with a timing signal .phi.c which is formed on the basis of a serial clock signal SC (not shown).
As shown in FIG. 5, a serial output operation for storage data in the dual-port memory is started by designating the row address r of a word line in M-ARY1 from which data is to be read out by address signals A0 to Ai, changing a data transfer control signal DT/OE to a low level, and then changing a row address strobe signal RAS to a low level. Slightly after the fall of the row address strobe signal RAS, a top column address c from which a serial output operation is to be started is designated in the form of address signals A0 to Ai, and then a column address strobe signal CAS is changed to a low level. Thus, in the dual-port memory, bits of data stored in memory cells of M-ARY1 which are coupled to the designated word line are read out for each of the rows and are transferred to the data register DR1 in response to the change of the data transfer control signal DT/OE from the low level to the high level. These bits of data thus read out are serially output through the serial input/output complementary common data line CDS1 in such a manner that the storage data corresponding to the column address c is in the forefront.
Such a dual-port member is described, for example, in the May 20, 1985, issue of "Nikkei Electronics", p. 209 to 211, and the Mar. 24, 1986, issue of "Nikkei Electonics", p. 254, Nikkei McGraw-Hill which are hereby incorporated by reference. For purposes of drawing simplification, FIG. 4 does not show details of the memory circuit construction since these are well-known, as discussed in the above-noted articles.
It has been clarified by the present inventors that the above-described dual-port memory suffers from the following problems. The storage data serial output operation in the serial output mode of the dual-port memory is started in response to the return of the data transfer control signal DT/OE to the high level as described above. Accordingly, to continueously execute such serial output operation, it is necessary to start a readout data transfer cycle for a subsequent serial output mode immediately before the storage data output operation in the previous serial output mode reaches the final column address n, and change the data transfer control signal DT/OE from the low level to the high level after the storage data output operation in the previous serial output mode has reached the final column address n as shown in FIG. 5. Moreover, the timing at which the data transfer control signal DT/OE is changed to the high level must be so set that a setup time Tts and a hold time Tth for the serial clock signal SC can be ensured, respectively, before and after of said timing. For this reason, it is essential to provide outside the dual-port memory a counter circuit for counting column addresses in accordance with the serial clock signal SC and a timing generator circuit for forming the data transfer control signal DT/OE and the like in accordance with relatively strict timing conditions such as those described above. This leads to a undesirable increase in the system cost. In addition, as the data transfer rate in video systems or the like is increased, it may become impossible to form the data transfer control signal DT/OE in accordance with the above-described strict timing conditions.